1. Field of the Invention
The present invention relates to an input receiver circuit used for transmitting a signal inputted from the outside to an internal circuit, more particularly to an input receiver circuit suitably used as an input circuit in semiconductor memory devices and the like.
2. Description of the Prior Arts
An input receiver circuit is installed in an integrated circuit (IC) such as a semiconductor memory device and receives a signal to be supplied to the integrated circuit from the outside, converts the received signal to an internal signal, and then supplies it to each of circuit blocks in the integrated circuit.
FIG. 1 shows the constitution of principal parts of a semiconductor memory device having the input receiver circuit. In FIG. 1, semiconductor memory device 1, mainly a signal input section thereof, is illustrated.
Semiconductor memory device 1 illustrated in FIG. 1 is constituted as an SDRAM (Synchronous Dynamic Random Access Memory). Semiconductor memory device 1 comprises flip-flop circuits 3 and 4; input receiver circuits 7.sub.1, 7.sub.2 and 7.sub.3 ; memory cell array 9 in which a plurality of memory cells are arranged; column decoder 23 for supplying column addresses to memory cell array 9 after decoding them; row decoder 22 for supplying row addresses to memory cell array 9 after decoding them; and sense amplifier 24 provided between memory cell array 9 and row decoder 22. Clock signal 101, address signal 102 and data signal 103 are supplied to this semiconductor memory device 1 from the outside thereof. These signals 101 to 103 are once received respectively by input receiver circuits 7.sub.1, 7.sub.2 and 7.sub.3, and transmitted to the internal circuits as internal clock signal 104, internal address signal 105 and internal data signal 106, respectively. Flip-flop circuits 3 and 4 latch internal address signal 105 and internal data signal 106, respectively, in synchronization with the leading edge of internal clock signal 104. Then, internal address signal 105 latched by flip-flip circuit 3 is inputted to column decoder 23 and row decoder 22, and internal data signal 106 latched by flip-flop circuit 4 is inputted to sense amplifier 24, whereby data reading/writing operations for memory cell array 9 are performed. As described above, an SDRAM for latching the data signal and the address signal in synchronization with the rise-up of the clock signal, that is, an SDRAM in which data strobe is performed in a single direction, shall be hereinafter referred to as an SDR (Single Data Rate)-SDRAM.
FIG. 2 shows the constitution of each of input receiver circuits 7.sub.1, 7.sub.2 and 7.sub.3. Each of these conventional input receiver circuit comprises N channel MOS (metal-oxide-semiconductor) transistors 11 to 14, P channel MOS transistors 15 and 16, and inverter 21.
Activation signal 10 is inputted to each gate of N channel MOS transistors 11 and 12, and the source of each of transistors 11 and 12 is grounded. N channel MOS transistors 11 and 12 are power cutting transistors which reduce power consumption by cutting off current flowing through the circuit, when the input receiver circuit is not operated, for example, in the case of a power down mode. Activation signal 10 is a signal which takes a ground potential when the input receiver circuit is made to be an inactive state.
N channel MOS transistor 13 receives at its gate the reference voltage V.sub.REF that is half that of the power source voltage, and the source thereof is connected to the drain of N channel MOS transistor 11. The source of P channel MOS transistor 15 is supplied with the power source voltage V.sub.CC and the drain thereof is connected to the drain of N channel MOS transistor 13. The gate and drain of P channel MOS transistor 15 are connected to each other. The source of P channel MOS transistor 16 is supplied with the power source voltage, and the gate thereof is connected to the gate of P channel transistor 15. The gates of P channel MOS transistors 15 and 16 are mutually connected by node 33. The drain of N channel MOS transistor 14 is connected to the drain of P channel MOS transistor 12, the gate thereof is applied with an input signal V.sub.IN, and the source thereof is connected to the drain of N channel MOS transistor 12. Inverter 21 receives the drain voltage of P channel MOS transistor 16, and inverts the logical level of the drain voltage of the P channel MOS transistor 16 to output it as an output signal V.sub.OUT. Inverter 21 is provided so that a signal amplitude ranging from the ground potential to the power source voltage is secured and the logical values of the input signal V.sub.IN and the output signal V.sub.OUT are made to be equal.
Next, an operation of the conventional input receiver circuit will be described with reference to FIG. 2.
As the voltage of the input signal V.sub.IN becomes higher, the on-resistance of N channel MOS transistor 14 is allowed to be smaller, so that the drain voltage of P channel MOS transistor 16 becomes lower. On the contrary, as the voltage of the input signal V.sub.IN becomes lower, the on-resistance of N channel MOS transistor 14 is allowed to be larger, so that the drain voltage of P channel MOS transistor 16 becomes higher.
When the reference voltage V.sub.REF becomes low, the on-resistance of N channel MOS transistor 13 becomes larger, so that the potential at node 33 becomes higher. For this reason, the gate voltages of P channel MOS transistors 15 and 16 become higher, so that the on-resistance of P channel MOS transistor 16 becomes larger, resulting in a lower drain voltage of P channel MOS transistor 16.
As described above, the input receiver circuit operates as a differential comparator for deciding the logical value of the input signal V.sub.IN using the reference voltage V.sub.REF as a reference. Specifically, when input signal V.sub.IN becomes higher than the reference voltage V.sub.REF, the output signal V.sub.OUT becomes high in level, and when the signal V.sub.IN becomes lower than the voltage V.sub.REF, the signal V.sub.OUT becomes low in level.
With reference to input/output voltages of the semiconductor memory devices, there has been standards such as a SSTL-2 interface defined by JEDEC (Joint Electronic Device Engineering Council-Electronic Industrial Association). In the SSTL-2 interface standard, a comparatively low voltage, for example, V.sub.REF =1.25.+-.0.1 V, V.sub.IN (max)/V.sub.IN (min)=V.sub.REF .+-.0.35 V. Here, the input voltage V.sub.IN becomes the lowest voltage, when V.sub.REF =1.15 V and V.sub.IN (min)=V.sub.REF -0.35 V. V.sub.IN (min) in this case is 0.8 V as is obtained from the following equation (1). EQU V.sub.IN (min)=V.sub.REF -0.35=1.15-0.35=0.8V (1)
When the threshold voltage of N channel MOS transistor 14 is assumed to be V.sub.TN and the voltage between the gate and source thereof is assumed to be V.sub.GS, the current I flowing from the drain of N channel MOS transistor 14 to the source thereof can be obtained by the following equation (2). EQU I=.beta./2.times.(V.sub.GS -V.sub.TN).sup.2 (2)
In the equation (2), .beta. is a coefficient expressed by .beta.=W.multidot..mu..multidot.C.sub.0 /L, W is the gate width, .mu. is the surface mobility of conduction electrons passing through the channel, C.sub.0 is the capacitance of the gate oxide film, and L is the gate length.
Here, even when the voltage between the source and drain of N channel MOS transistor 12 is neglected, V.sub.GS is equal to 0.8 V as is obtained from the equation (1) because V.sub.GS is approximately equal to V.sub.IN. When the input receiver circuit is designed assuming that threshold voltage V.sub.TN of N channel MOS transistor 14 is 0.6 V, the actual threshold voltage V.sub.TN varies at a range of about .+-.0.15 V due to the unevenness of the ion implantation amount in the fabricating processes. Therefore, in the worst case, the threshold voltage V.sub.TN will be equal to 0.75 V. The current I is expressed by the following equation (3) when these values are substituted into the equation (2). EQU I=.beta./2.times.(0.8-0.75).sup.2 (3)
Referring to the equation (3), since (V.sub.GS -V.sub.TN) is as small as 0.05, also the value of the current I becomes small. Actually, since the voltage between the source and drain of N channel MOS transistor 12 is not equal to zero, VGS &lt;0.8 V is satisfied, so that the current I becomes further smaller. For this reason, in N channel MOS transistor 14, the gain for the input signal V.sub.IN can not almost be obtained.
FIG. 3 is a graph showing the results of the changes in the propagation time with respect to the reference voltage V.sub.REF, which are obtained by simulations, when the input signal V.sub.IN takes the minimum value in the case of the worst V.sub.TN in the conventional receiver circuit of FIG. 2. In the graph of FIG. 3, the solid line represents the propagation time when the input signal V.sub.IN rises up, and the broken line represents the propagation time when the input signal V.sub.IN falls. Here, the propagation time is a period of time in which the output signal V.sub.OUT changes from high level to low level after the input signal V.sub.IN transits from high level to low level. Or, the propagation time is a period of time in which the output signal V.sub.OUT changes from low level to high level after the input signal V.sub.IN transits from low level to high level. The difference between the propagation time when the input signal changes from high level to low level and the propagation time when it changes from low level to high level is a propagation time difference.
Referring to the graph of FIG. 3, when the reference voltage V.sub.REF is 1.15 V, the propagation time at the rise-up of the input signal is 1.26 ns and the propagation time at the fall of the input signal is 0.87 ns. In this case, the propagation time difference is 0.39 ns (.apprxeq.0.4 ns) obtained by subtracting 0.87 from 1.26. When the reference voltage V.sub.REF is 1.15 V, the propagation time difference is about 0.4 ns, and the propagation time when the input signal changes from low level to high level is shorter than the propagation time when it changes from high level to low level by 0.4 ns.
To shorten the propagation time difference, it is satisfactory that the standard value of the threshold voltage of N channel MOS transistor 14 (see FIG. 2) is made to be further lower than 0.6 V. However, when the threshold value V.sub.TN of N channel MOS transistor 14 is lowered, threshold values of other N channel MOS transistors formed in the same fabricating processes are also lowered. If these N channel MOS transistors are used in locations where a voltage is applied in a stand-by state, a sub-threshold current of the MOS transistor can not be neglected, resulting in an increase in a leak current. For this reason, this leads to the fact that the semiconductor memory device can not satisfy a specification for the stand-by current of the whole of the semiconductor memory device. On the other hand, the foregoing problem can be solved when fabrication processes for forming N channel MOS transistor are exclusively provided and only the threshold voltage of N channel MOS transistor 14 is lowered while leaving threshold voltages of other N channel MOS transistors as they are. However, in order to achieve this, the sorts of the threshold values to be set in a process design increase and the number of processes increases, leading to an increase in cost of the semiconductor memory device.
FIG. 4 is a timing chart showing a relation between clock signal 101 and data signal 103 in the foregoing conventional SDR-SDRAM which latches the data signal and the address signal at the leading edge of the clock signal. Here, a frequency of clock signal 101 shall be set to 100 MHz. Periods of both of clock signal 101 and internal clock signal 104 are 10 ns.
In the SDR-SDRAM, internal data signal 103 is latched by the rise-up of internal clock signal 104 in flip-flop circuit 4. Here, in order to allow flip-flop circuit 4 to securely latch internal data signal 106 at the leading edge of internal data signal 104, internal data signal 106 must be kept so as not to make a change, for a certain period of time immediately before and after the rise-up of internal clock signal 104. Thus, a set-up time 30 in which internal data signal 106 must be kept before internal clock signal 104 rises up and a hold time 31 in which internal data signal 106 must be kept after internal clock signal 104 rises up are required for flip-flop circuit 4. A total of the set-up time and the hold time is called a window time of flip-flop circuit 4. The foregoing set-up time, the hold time and the window time are defined for each of internal clock signal 104 and internal data signal 106, and the set-up time, the hold time and the window time are similarly defined also for clock signal 101 and data signal 103.
As shown in FIG. 4, a time in which data signal 103 must be kept before clock signal 101 rises up is set-up time 30, and a time in which data signal 103 must be kept after clock signal 101 rises up is hold time 31. The total time of set-up time 30 and hold time 31 is window time 32 of data signal 103. Window time 32 of data signal 103 is a time obtained by adding the propagation time difference of input receiver circuits 7.sub.1 to 7.sub.3 to the window time of flip-flop circuit 4.
Next, the situations of changes of the window time by the propagation time difference of the input receiver circuits will be described using FIGS. 5A and 5B. FIG. 5A is a timing chart in the case where high level data is latched at the leading edge of the clock signal, and FIG. 5B is a timing chart in the case where low level data is latched at the leading edge of the clock signal. Here, t.sub.R represents the propagation time at the rise-up of the clock signal 101; t.sub.F, the propagation time at the fall of the internal data signal 106; t.sub.S, the set-up time of data signal 103; t.sub.H, the hold time of data signal 103; t.sub.SI, the set-up time of flip-flop circuit 4; and t.sub.HI, the hold time of flip-flop circuit 4. In order to make the concrete description, as described above, the propagation time difference (t.sub.F -t.sub.R) of the input receiver circuit in the worst case at the range of the specification values shall be 0.4 ns as shown in FIG. 3. The set-up time t.sub.S and the hold time t.sub.H when high level data signal 103 is latched by the rise-up of clock signal 101 are respectively obtained by the following equations (4) and (5), as is illustrated in FIG. 5A. EQU t.sub.S =t.sub.SI +t.sub.R -t.sub.R =t.sub.SI (4) EQU t.sub.H =t.sub.HI +t.sub.R -t.sub.F =t.sub.HI -0.4 (5)
As is understood from the equation (4), the set-up time t.sub.S of data signal 103 is equal to the set-up time t.sub.SI of flip-flop circuit 4, and it is not degraded by the input receiver circuits. Moreover, as is understood from the equation (5), the hold time t.sub.H of data signal 103 is shorter than the hold time t.sub.HI of flip-flop circuit 4 by 0.4 ns, and it is not also degraded by the input receiver circuits.
On the other hand, the set-up time t.sub.S and the hold time t.sub.H when low level data signal 103 is latched at the time of the rise-up of clock signal 101 are respectively obtained by the following equations (6) and (7), as is illustrated in FIG. 5B. EQU t.sub.S =t.sub.SI +t.sub.R -t.sub.R =t.sub.SI +0.4 (6) EQU t.sub.H =t.sub.HI +t.sub.R -t.sub.F =t.sub.HI (7)
As is understood from the equation (6), the set-up time t.sub.S of data signal 103 is longer than the set-up time t.sub.SI of flip-flop circuit 4 by 0.4 ns, and it is degraded by propagation time difference of the input receiver circuits. Moreover, as is understood from the equation (7), the hold time t.sub.H of data signal 103 is equal to the hold time t.sub.HI of flip-flop circuit 4, and it is not degraded by the input receiver circuits.
In the case where the propagation time difference (t.sub.F -t.sub.R) of the input receiver circuit is 0.4 ns, the set-up time t.sub.S of data signal 103 is longer than the set-up time t.sub.SI of flip-flop circuit 4 and becomes worse only when low level data signal 103 is latched at the time of the rise-up of clock signal 101. Specifically, the window of data signal 103 is longer than the window time of flip-flop circuit 4 by 0.4 ns that is the propagation time difference and it becomes worse.
In the foregoing descriptions, the case where the propagation time t.sub.F at the fall of the input receiver circuit is longer than the propagation time t.sub.R at the rise-up thereof was described. On the contrary, in the case where the time t.sub.R is longer than the time t.sub.F, the hold time is degraded when high level data signal 103 is latched at the time of the rise-up of clock signal 101,
As described above, when data signal 103 is latched only at the leading edge of clock signal 101 like the SDR-SDRAM, the window time of data signal 103 becomes longer than the window time of flip-flop circuit 4 by the propagation time, and becomes worse.
Besides the foregoing SDR-SDRAM, there have been some SDRAMs which each of uses a data latch signal other than the clock signal for latching the data signal and latches the data signal at both of its rise-up and fall. The SDRAM performing such bi-directional data strobe is called a DDR (Double Data Rate)-SDRAM. In the case where the conventional input receiver circuit is used in the DDR-SDRAM, the degradation of the window time due to the propagation time difference becomes more significant.
FIG. 6 shows the structure of a semiconductor memory device that is the DDR-SDRAM. Semiconductor memory device 41 shown in FIG. 6 differs from semiconductor memory device 1 shown in FIG. 1 in that input receiver circuit 7.sub.4, buffer 6, inverter 8, flip-flop circuit 5, and multiplexer 25 are newly added and data latch signal 107 is inputted from the outside.
Data latch signal 107 is once inputted to input receiver circuit 7.sub.4, and outputted therefrom as internal data latch signal 108. Internal data latch signal 108 is supplied to flip-flop circuit 4 via buffer 6, and supplied also to flip-flop circuit 5 via inverter 8. Buffer 6 generates the delay time equal to that of inverter 8, and is provided so that it compensates the delay time of inverter 8 in order to make the compensated delay time coincide with the timing of internal data latch signal 108 which is inputted to flip-flop circuits 4 and 5. Flip-flop circuit 4 latches internal data signal 106 at the timing when internal data latch signal 108 rises up, and flip-flop circuit 5 latches internal data signal 106 at the timing when internal data signal 108 falls. Multiplexer 25 multiplies the signal latched by flip-flop circuit 4 with the signal latched by flip-flop circuit 5, and outputs the calculation result to sense amplifier 24.
An operation of this DDR-SDRAM will be described with reference to the timing chart shown in FIG. 7. Here, the frequency of clock signal 101 shall be 100 MHz similarly to that described in FIG. 4, and the interval time between the rise-up and the fall of data latch signal 107 shall be 5 ns.
Internal data signal 106 is latched at intervals of 5 ns at the leading edge and the trailing edge of internal latch signal 108 in flip-flop circuits 4 and 5, respectively. In the DDR-SDRAM, since the intervals for latching internal data signal 106 are short, when the frequency of clock signal 101 is, for example, 100 MHz, the window time is about 1.5 ns.
Next, descriptions will be made on how the window time changes depending on the propagation time difference of the foregoing input receiver circuit when the input receiver circuit is used for the DDR-SDRAM. Here, in order to make the concrete description, the propagation time difference (t.sub.F -t.sub.R) of the input receiver circuit shall be 0.4 ns, as is shown in FIG. 3, in the worst case at the range of the specification values. An operation in the case where data signal 103 at high or low level is latched at the leading edge of clock signal 101 is the same as the operation shown in FIGS. 5A and 5B when the clock signal is only replaced by the data latch signal. Therefore, the window time between data latch signal 107 and data signal 103 becomes longer by 0.4 ns by the input receiver circuit and becomes worse.
An operation in which data signal 103 is latched at the trailing edge of data latch signal 107 will be described using FIGS. 8A and 8B. FIG. 8A show the timing chart when data signal at high level is latched at the trailing edge of the data latch signal, and FIG. 8B shows the timing chart when data signal at low level is latched at the trailing edge of the data latch signal.
The set-up time t.sub.S and the hold time t.sub.H when data signal 103 at high level is latched at the trailing edge of data latch signal 107 are obtained by the following equations (8) and (9), as is illustrated in FIG. 8A. EQU t.sub.S =t.sub.SI +t.sub.R -t.sub.F =t.sub.SI -0.4 (8) EQU t.sub.H =t.sub.HI +t.sub.R -t.sub.R =t.sub.HI (9)
As is understood from the equation (8), the set-up time t.sub.S of data signal 103 is shorter than the set-up time t.sub.SI of flip-flop circuit 5, and it is not degraded by the input receiver circuit. As is understood from the equation (9), the hold time t.sub.H of data signal 103 is equal to the hold time t.sub.HI Of flip-flop circuit 5, and it is not degraded by the input receiver circuit.
The set-up time t.sub.S and the hold time t.sub.H when data signal 103 at low level is latched at the trailing edge of data latch signal 107 are obtained by the following equations (10) and (11), as illustrated in FIG. 8B. EQU t.sub.S =t.sub.SI +t.sub.F -t.sub.R =t.sub.SI (10) EQU t.sub.H =t.sub.HI +t.sub.R -t.sub.R =t.sub.HI +0.4 (11)
As is understood from the equation (10), the set-up time t.sub.S of data signal 103 is equal to the set-up time t.sub.SI of flip-flop circuit 5, and it is not degraded by the input receiver circuit. As is understood from the equation (11), the hold time t.sub.H of data signal 103 is longer than the hold time t.sub.HI of flip-flop circuit 5 by 0.4 ns, and it is degraded by the input receiver circuit.
As described above, in the case where the propagation time difference (t.sub.F -t.sub.R) of the input receiver circuit is 0.4 ns, the set-up time t.sub.S of data signal 103 is longer than the set-up time t.sub.SI of flip-flop circuit 4 and is degraded when data signal 103 at low level is latched at the leading edge of data latch signal 107. Furthermore, when data signal 103 at low level is latched at the trailing edge of data latch signal 107, the hold time of data signal 103 becomes longer than the hold time of flip-flop circuit 5, and it becomes worse.
Specifically, the window time of data signal 103 is longer than the window time of flip-flop circuit 4 by 0.8 ns, twice 0.4 ns that is the propagation time difference, and it becomes worse.
The above descriptions was made for the case in which the propagation time t.sub.F at the fall of the input receiver circuit is longer than the propagation time t.sub.R at the rise-up thereof. In the case contrary to this, the set-up time becomes longer and is degraded when data signal 103 at high level is latched at the trailing edge of data latch signal 107, and the hold time is degraded when data signal 103 at high level is latched at the leading edge of the data latch signal 107.
As described above, when the input receiver circuit exhibiting the propagation time difference of 0.4 ns is used for the DDR-SDRAM, the window time between data signal 103 and data latch signal 107 becomes longer than the window time of flip-flop circuit 4 by 0.8 ns that is twice the propagation time difference. Considering other factors such as differences of pins supplied with the data signal and a temperature dependency, a margin of the window time for the typical value of 1.5 ns reduces. Then, the possibility that the window time exceeds the standard due to variations during manufacturing becomes large.
After all, in the foregoing input receiver circuit, the propagation time difference between the rise-up and the fall of the input signal is large. When the input receiver circuit is applied to, for example, the SDRAM, there has been a problem that the margin for the window time defined by the standard can not be secured.